SW-QUARTUS-SE-FIX

989-SWQUARTUSSEFIX
SW-QUARTUS-SE-FIX

製造商:

說明:
開發軟體 Quartus Prime Standard Edition - Fixed node subscription supporting all devices on Windows platforms. Includes subscription software updates for one year. (c)

壽命週期:
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Altera SW-ONE-QUARTUS
Altera
開發軟體 Quartus Prime Software

商品屬性 屬性值 選擇屬性
Altera
產品類型: 開發軟體
送貨限制:
 Mouser目前不在您的地區出售本產品。
RoHS:
Software
FPGAs, SoCs, and CPLDs
品牌: Altera
組裝國家: Not Available
擴散國: Not Available
原產國: Not Available
描述/功能: Fixed license for Windows
產品類型: Development Software
系列: Quartus
原廠包裝數量: 1
子類別: Embedded Solutions
公司名稱: Quartus
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所選屬性: 0

CNHTS:
8523499000
USHTS:
8523494000
TARIC:
8523499000
MXHTS:
85234999
ECCN:
5D992.c

SoC FPGA Family

Altera SoC FPGAs integrate an Arm-based hard processor system (HPS) consisting of processors, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The devices combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable Arm-based SoC FPGAs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA.

Quartus® Prime Design Software

Altera Quartus® Prime Design Software delivers improvements across the three key areas designers care about most performance, productivity, and usability. It supports the latest Agilex™ 7 and Agilex 5 FPGA and SoC families, ensuring a seamless development experience for cutting-edge applications. Coming in an upcoming release, support for the new Agilex 3 FPGAs and SoCs family and new MAX 10 FPGA package options that squeeze 485 I/Os into a 19 x 19mm2 sized package. Fast compile times allow designers to accelerate FPGA development, with larger designs benefiting from even greater reductions. Enhanced compiler optimizations also significantly reduce peak virtual memory requirements, ensuring most FPGA designs compile within 64GB of memory.