IS43LR32160C-6BLI

ISSI
870-IS43LR32160C6BLI
IS43LR32160C-6BLI

製造商:

說明:
DRAM 512M, 1.8V, 166Mhz Mobile DDR

ECAD模型:
下載免費的庫載入器,為ECAD工具轉換此文件。瞭解更多關於 ECAD 型號的資訊。

庫存量: 395

庫存:
395 可立即送貨
工廠前置作業時間:
8 週 工廠預計生產時間數量大於所顯示的數量。
最少: 1   多個: 1   上限: 200
單價:
HK$-.--
總價:
HK$-.--
估計關稅:

Pricing (HKD)

數量 單價
總價
HK$75.87 HK$75.87
HK$70.53 HK$705.30
HK$68.39 HK$1,709.75
HK$66.83 HK$3,341.50
HK$65.51 HK$6,551.00

商品屬性 屬性值 選擇屬性
ISSI
產品類型: DRAM
RoHS:  
SDRAM Mobile - LPDDR
512 Mbit
32 bit
166 MHz
BGA-90
16 M x 32
6 ns
1.7 V
1.95 V
- 40 C
+ 85 C
IS43LR32160C
Tray
品牌: ISSI
組裝國家: Not Available
擴散國: Not Available
原產國: TW, CN
濕度敏感: Yes
安裝風格: SMD/SMT
產品類型: DRAM
原廠包裝數量: 240
子類別: Memory & Data Storage
電源電流 - 最大值: 60 mA
公司名稱: RLDRAM2
每件重量: 167.700 mg
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所選屬性: 0

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CNHTS:
8542329000
USHTS:
8542320028
JPHTS:
854232021
MXHTS:
8542320201
ECCN:
EAR99

IS43LR16800F 2Mx16 Mobile DDR SDRAM

ISSI IS43LR16800F 2Mx16 Mobile DDR SDRAM is 134,217,728 bits Mobile Double Data Rate (DDR) Synchronous DRAM (SDRAM) organized as 4 banks of 2,097,152 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.

Mobile DDR SDRAM

ISSI Mobile DDR SDRAM is organized as 4 banks of 16,777,216 words x 16 bits and uses a double-data-rate architecture to achieve high-speed operation. The Data Input/Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. ISSI Mobile DDR SDRAM offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.