Name: ISSI IS43R16320D-6BLI
Brand: ISSI
SKU: 870-IS43R16320D-6BLI
Price: 109 HKD
Availability: OutOfStock

說明：

DRAM 512M (32Mx16) 166MHz 2.5v DDR SDRAM

Pricing (HKD)

數量	單價	總價
	HK$109.00	HK$109.00
	HK$101.19	HK$1,011.90
	HK$98.15	HK$2,453.75
	HK$95.76	HK$4,788.00
	HK$93.46	HK$9,346.00
	HK$90.42	HK$17,179.80
	HK$88.12	HK$50,228.40
	HK$85.90	HK$97,926.00
2,660	報價

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商品屬性	屬性值	選擇屬性
製造商:	ISSI
產品類型:	DRAM
RoHS:
類型:	SDRAM - DDR
存儲容量:	512 Mbit
數據匯流排寬度:	16 bit
最高時鐘頻率:	166 MHz
封裝/外殼:	BGA-60
組織:	32 M x 16
存取時間:	6 ns
電源電壓 - 最小值:	2.3 V
電源電壓 - 最大值:	2.7 V
最低工作溫度:	- 40 C
最高工作溫度:	+ 85 C
系列:	IS43R16320D
封裝:	Tray
品牌:	ISSI
組裝國家:	Not Available
擴散國:	Not Available
原產國:	TW, CN
濕度敏感:	Yes
安裝風格:	SMD/SMT
產品類型:	DRAM
原廠包裝數量:	190
子類別:	Memory & Data Storage
電源電流 - 最大值:	370 mA

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所選屬性: 0

篩選文檔:

規格書

IS43R16320D-6BLI 規格書 (PDF)

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CNHTS:: 8542319090
USHTS:: 8542320028
JPHTS:: 8542320216
KRHTS:: 8542321010
MXHTS:: 8542320299
ECCN:: EAR99

IS43R32800D 8Mx32 256-Mbit DDR SDRAM

ISSI IS43R32800D 8Mx32 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64MB to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages.

DDR SDRAM

ISSI 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages. The device is available in 8-bit, 16-bit, and 32-bit data word sizes. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. ISSI 512-Mbit DDR SDRAM commands are registered on the positive edges of CLK.